\doxysection{ADC\+\_\+\+Common\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_a_d_c___common___type_def}{}\label{struct_a_d_c___common___type_def}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___common___type_def_ac38e24f600f9e134a54a0c43b976a4f4}{CSR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___common___type_def_a5206a0915a426980291c55c79db38890}{RESERVED}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___common___type_def_aee6d4af7571a1bad2fec9e7b53733277}{CCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___common___type_def_a6f7399bf70f677ef5de46a3038f414e1}{CDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___common___type_def_a8ee71d207d53fc1cfb5e45acb59e181e}{CDR2}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_a_d_c___common___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_a_d_c___common___type_def_aee6d4af7571a1bad2fec9e7b53733277}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}!CCR@{CCR}}
\index{CCR@{CCR}!ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR}{CCR}}
{\footnotesize\ttfamily \label{struct_a_d_c___common___type_def_aee6d4af7571a1bad2fec9e7b53733277} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Common\+\_\+\+Type\+Def\+::\+CCR}

ADC common control register, Address offset\+: ADC1/3 base address + 0x308 \Hypertarget{struct_a_d_c___common___type_def_a6f7399bf70f677ef5de46a3038f414e1}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}!CDR@{CDR}}
\index{CDR@{CDR}!ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CDR}{CDR}}
{\footnotesize\ttfamily \label{struct_a_d_c___common___type_def_a6f7399bf70f677ef5de46a3038f414e1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Common\+\_\+\+Type\+Def\+::\+CDR}

ADC common regular data register for dual Address offset\+: ADC1/3 base address + 0x30C \Hypertarget{struct_a_d_c___common___type_def_a8ee71d207d53fc1cfb5e45acb59e181e}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}!CDR2@{CDR2}}
\index{CDR2@{CDR2}!ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CDR2}{CDR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___common___type_def_a8ee71d207d53fc1cfb5e45acb59e181e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Common\+\_\+\+Type\+Def\+::\+CDR2}

ADC common regular data register for 32-\/bit dual mode Address offset\+: ADC1/3 base address + 0x310 \Hypertarget{struct_a_d_c___common___type_def_ac38e24f600f9e134a54a0c43b976a4f4}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_a_d_c___common___type_def_ac38e24f600f9e134a54a0c43b976a4f4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Common\+\_\+\+Type\+Def\+::\+CSR}

ADC Common status register, Address offset\+: ADC1/3 base address + 0x300 \Hypertarget{struct_a_d_c___common___type_def_a5206a0915a426980291c55c79db38890}\index{ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!ADC\_Common\_TypeDef@{ADC\_Common\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_a_d_c___common___type_def_a5206a0915a426980291c55c79db38890} 
uint32\+\_\+t ADC\+\_\+\+Common\+\_\+\+Type\+Def\+::\+RESERVED}

Reserved, ADC1/3 base address + 0x304 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
